A Microprocessor Implementation of a Controller for a Dectape Transporter

In the work of this thesis, microprocessor , based software and hardware have been designed to p~rform the functions of the PDP 9 Dectape controller. For 8-bit data transfer, seven functions were implemented in software that simulate the move, stop, search, read, write and formating functions of the PDP 9 Dectape controller. The hardware is designed to interface the Dectape Transport with the microprocessor, as well as to amplify and temporarily store signals. The new controller is implemented with an inexpensive Motorola 6800 microcompuier. Hence, the Dectape transports can be used with any computer or with special, exp~rim~ntal apparatus. Sixteen-bit transfer was also attempted but the resulting system still requires more testing and development.

The PDP -9 TC02 Controller is used to direct the TU55 Transport to read forward or in reverse. to write forward or in reverse. to stop and to go [1.2,3]. as well as to write the timing and mark tracks on the tape(formating). The hardware consists of shift registers to temporarily store the word to be read or to be written, decoders to detect specific codes in the tape, interfaces, as vell as aaplifiers to aatch the signals from the tape to the signals which are required for the microprocessor.
The microprocessor based controller can identify each one of the codes prevritten in the tape, count them, and select the exact location in the tape for reading or writing. The controller can cause the tape to stop at a location specified by the program. It can change the direction of motion of the tape at any desired time or block, make the tape go from one end to the other, or start the read or write functions whether in forward or in reverse.
The controller can also, as the PDP -9 does, format the tape with the number of blocks and words desired.
7 THE TC02 CONTROLLER [2] A typical PDP 9 tape system consists of one TC02 controlle~ and up to eight tape transports.
The controller uses the Manchester phase recording technique rather than an amplitude sensing technique; thus, the tape speed need not be a precisely controlled parameter. Actually, the speed varies ±20 I, depending upon the diameter of the tape pack on the reel.
The controller uses a 10 -track read-write head.
Tracks are arranged in five nonadjacent redundant channels: a timing channel. a mark channel, and three information channels.
The timing ani mark track channels control the timing of operations within the TC02 controller unit and establish the format of data contained on the information channels.    I  I  I  I  I  I  I  I  I  I  I  I  I   Ill ~ ""0-21•~-11   I  I  I  I  I  I  I  I  I  I  I  I  I   Ul DAT& C-•I)  '"' L l•ILI II I l I " IL111i l I" I l i11iLI" IL  I  I  I  I  I  I  I  I  I  I  I  I  I   I  I  I  I  I  I  I  I  I  I  I  I  As an example of how to use the PDP -9 instructions to program the controller, the following program searches, reads and writes 10 words, from location 100 to 1012 in the PDP -9 memory.

HARDWARE IMPLEMENTATION
The following is a description of the hardware designed to interface the 6800 Dectape controller with the PDP -9 Transporter. First there is a brief discussion of the · PDP -9 read/write amplifier and the circuit designed to substitute it, after that, there is a discussion of the interface and registers.

READ AMPLIFIER
The TC02 amplifier is a high gain differential aaplifier with a positive feedback. When a signal of either polarity is sensed by the head, the read amplifier outputs switch inmediately (see fig. t3). [2] The read amplifier outputs o and v, are standard logic ievels of -3V and ground. When input E is more positive than input D. V is asserted at ground and U is negative; when D is more positive. the output levels reverse. Because of positive feedback. the read amplifier oscillates in the absence of input signals. [2] The inputs coming from the heads are differential signals.
The following is a fast view of the operational amplifier and the comparator.

20
An operational amplifier as shown in fig. t7 is a direct-coupled device with differential inputs and a single-ended output. (12,13,14] The amplifier responds only to the difference in voltage between the two input terminals, not to their common potential.
A positive going signal at the inverting input, while holding the other input at ground produces a negative going signal at the output, whereas the same signal at the non inverting input produces a positive going signal at the output. With a differential input voltage Ein, the output voltage Eo will be AvoEin, where Avo is the gain of the The fig. 18 shows a basic non inverting amplifier.

Rf
.__-------4+ A comparator circuit is one that provides an indication of the relative state of two input potentials.
The comparator output will indicate whether the input signal is above or below the reference potential. Op Amps may be used as comparators, but a true comparator differs from an operational amplifier in several respects. A comparator has a slew rate as much as 100 times faster than that of an Op Amp. It is not frequency compensated and thus would probably be unstable if negative feedback were applied. the CMRR (Common ~ode Rejection Ratio) and PSRR (Power Supply Rejection Ratio ) are not always specified in comparators.
A basic comparator circuit is shown in fig. 19 - to change the output from one stat~ to the other is quite small, essentially: Since this voltage is but a few hundred microvolts, the doainatin9 factor that determines the exact threshold is the offset voltage of the amplifier, which may be as great as ±10 mV.
For this reason precision comparators should be nulled, so that when the output is zero, the input differential voltage will be as close to zero as practical.
Furthermore, any source resistances in the input path should be selected so as to minimize the offse~ voltage.

ZERO CROSSING DETECTOR
A zero crossing detector is a comparator with the inverting lead grounded and the input signal applied to the noninverting lead. When the input voltage is slightly aore positive than 24 the zero reference voltage on the inverting iead, the output slews to positive saturation. Conversely, when the input signal voltage is slightly more negative than the reference voltage (zero volts)• the output slews to negative saturation. The crossover point is at the zero reference voltage; thus it is called a zero crossing detector. [ 14] zero crossing detectors are subject to chatter at the crossing point. This usually occurs vhen a noise voltage is present on the signal. In fig. 110, a chatter situation is illustrated. (14] "Chatter" at zero crossing In order to control the chattering, an hysteresis loop is introduced d h h · f · 1 aroun t e comparator as s own in ig. I 1.
[ 14]  By introducing R2, positive feedback is developed across R1. If the output is high, R2 will feedback a signal which will be added to the reference voltage. This voltage increment will be: aaking the new reference voltage.
The circuit was tested. but its performance was not as expected because little hysteresis did not get rid of the noise and large hysteresis changed the output signala Instead of the hysteresis, a low pass filter was designed and proved to work well.
The read amplifier designed is shown in fig. #12.

IRITE AMPLIFIER
The write amplifier used in the TC02 controller, is a high current gain amplifier which has ±3V standard PDP -9 input voltage and a output of 0 to -15V with a 180 mA current capacity. (2) A circuit was designed that produces the same output signal as that of the PDP -9 write amplifier. The first stage works as an interface between the TTL and the PDP -9 voltages and currents necessary to drive the write amplifier.
The second stage is a current amplifier that sinks 180 mA when the transistor is in saturation. Then, the maxiaum power disipation is (see fig. 114 ): A 1W NPN transistor was choosen for the last stage, the base current (for hfe=100) will be 1.80 mA and to assure this current a maximum base resistor of: The information coming from the tape is a train of pulses that have to be loaded into the microprocessor memory synchronized with the time information and the mark codes also coming from the tape at the same time.
The read out of the timing pulses, is used to synchronize the entire system. Fig. #16 shows photograps of the timing pulse generated by the circnit designed in comparison with the time signal generated in the PDP -9 controller.      The circuit designed to generate the timing pulses and the word assembler for the formating of the tape(timing and mark tracks) is shown in fig. 12q.       finally replaced by a better design using an input low pass filter, which worked fine when experimentally tested.
The interference problem resulted because of the physical proximity of the wires coming from the read/write heads.
In the original PDP -9 read/write amplifier, a ground is provided all around the board and precau~ions had been taken to shield the conductors to the heads. A good and a stable ground solved this problem.
The second major problem was an apparen~ interference between the tiaing and mark track that distorts the mark track in each positive transition of the ~ime track. This problem, that probably produced the false readings, vas solved later using a pull up resistor of 1K ohms in the output of the read buffers !C8T97P. The lack of specification data about this chip did not allow an early solution to the problem.
Tape degradation due to excessive use and frequent handling caused a delay in the work. ls a matter of fact.
several reformatings were necessary to achieve the correct read out.