Design and Implementation of 8 Bit Successive Approximation ADC at 1MHZ

Successive Approximation Analog to Digital converters (ADCs) are very popular for reasonably quick conversion time and good resolution yet moderate circuit complexity. This thesis describes the design and implementation of a Successive Approximation ADC with 8-bit resolution at lMHz speed in 0.5 um CMOS technology. Design, architecture, methodology and performance of the proposed ADC are presented. The main features of the Successive Approximation (SAR) ADC architecture designed are very low power dissipation and small chip area because of the compar' atively simple circuit implementation. The internal Digital to Analog Converter (DAC) is the most important block of the SAR ADC. Division of Charge implementation was used to realize the DAC to minimize the short-comings of the conventional charge-redistribution implementation. The SAR ADC was realized using Switched Capacitor circuitry. The hardware implementation of the schematic was done in MAGIC and the functionality of the ADC was tested in HSPICE. A test chip was fabricated and received for verification of the simulation results .


Subranging or Two-Step
The working of charge division by 2 circuit . . . 35 The implemented architecture of the SAR ADC 38 The conversion process of the SAR ADC . 39 The non-overlapping nature of the clocks . 41 The The circuit implementation of the Accumulator 44 The divide by 2 circuit implementation . . . . . 47 Simulation results of the accumulator and the divide by 2 cicuit 48 The circuit implementation of the transconductance op-amp . . 49 Simulation results with the performance metrics of the op-amp . 52 The circuit implementation of Latched Comparator. . 53 The simulation results of the comparator . 54 The FFT of Spice Extracted File .
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Introduction
The growth in Digital Computing and Digital Signal Processing in the electronics world is usually referred as " the world is becoming digital day by day." Digital circuits are less sensitive to the noise and exhibit more robustness to the increasing variations of the process and supply voltages, they also allow comparatively easier test automation when compared to the analog circuits. Hence the informatio\1 is being increasingly stored, processed and communicated in the digital domain [1]. In our physical environment, naturally occurring signals are analog, hence a device that converts these analog signals to digital form is essential. An Analog to Digital Converter (ADC) converts a continuous signal into binary information. Thus, Analog to Digital Converters and their counterparts the Digital to Analog Converters are critical building blocks or sometimes even bottle necks in many applications.
An overwhelming variety of ADCs exist in the market today, with different resolutions, bandwidths, accuracies, architectures, packaging, power requirements, and temperature ranges, as well as variety of specifications, covering a broad range of performance needs. There also exists a variety of applications in Data Acquisi-

tion, Precision Measurement Applications, Communications, Instrumentation and
Interfacing for Signal Processing etc. Depending upon the application, there is always a "best choice" of a particular type of ADC because of a clear cut advantage rather than any available ADC model. Thus, there is always an increasing need for further improvement of available ADC models. 1 1 Goal

1.
The objective of this thesis is to design and implement an 8-bit Successive  [2].
Most of the previous implementations of the SAR ADCs used the conventional R-2R architecture to implement the internal DAC [2]. The R-2R architecture inherently suffers from DNL (Differential Non-Linearity) and INL (Integral Non-Linearity) errors, due to the mismatch in the resistors comprising the R-2R ladder.

Introduction to Analog to Digital Converters
The basic definition of an ideal Analog to Digital Converter (ADC) and its transfer curve are presented in the first part of chapter. The second part of the chapter classifies and defines different ADC performance parameters. These parameters evaluate ADC's performance and thus help the designer to choose an appropriate architecture for a specific application.

IdeAl Analog to Digital Converter (ADC)
The block diagram representing a basic Analog to Digital Converter is shown in Figure 1. In the figure, Bout is the digital output word, Vin and Vref are the analog input and the reference signals respectively. The analog input and the digital output word are related by the following equation.

Where
VisB is defined as the change corresponding to a single Least Significant Bit(LSB) change.
Vin Bout ADC Vref _ _ _ ~J Figure l. Block diagram representing a Analog to Digital Converter (ADC) [1] 4 The input-output transfer curve of an ideal 3-bit ADC is shown in Figure 2(a).
Since the input signal is a continuous signal and the output is discrete, the transfer curve of the ADC resembles that of a staircase. The Figure  • Quantization Error: As a range of valid input values produce the same digital output word, signal ambiguity results and is referred to as the Quantization error Q e .This error is defined as the difference between the actual analog input and the value of the output given in voltage [3].
Where D is the Digital output code and VLssis the value of 1 LSB in volts. Figure 2(b) iUU11trates the Quantization error of an ideal 3-bit ADC .

A D C Specifications
The Performance measures of an ADC can be classified into three categories: Static, Dynamic and Frequency Domain. The following sections detail them.  • Gain Error: The Gain error is defined to be the difference at the full-scale value between the ideal and actual curves when the offset error has been reduced to zero [1] . The Gain error for an ADC can be mathematically   Figure 4. Transfer Curve illustrating Gain error [2] 8 • Accuracy: The absolute accuracy of a converter is defined to be the difference between the expected and actual transfer responses [1] . The absolute accuracy includes the offset, gain and the linearity errors.   [2] 10 Vin Vref Vin Vref • Differential Nonlinearity Error(DNL) : Differential nonlinearity error is difference between the actual code width of a non-ideal converter and the ideal converter. Figure 6 illustrates the DNL error.    The basic idea of this thesis is to design and implement a Successive Approximation ADC , hence popular Successive Approximation ADC architectures are discussed in the second part of the chapter.

Different ADC Architectures
As already mentioned , Data converters are classified into two main categories, Nyquist rate data converters and Over sampling data converters based on the sampling rate. Flash ADC , Pipelined ADC , Successive Approximation ADC and Integrating ADC fall under Nyquist rate Data converters. Sigma-Delta ADCs fall under the Over sampling data converter category. Each has benefits that are unique to that architecture and span the spectrum of high speed and resolution.

Flash ADCs
Flash ADC 's, also known as the parallel ADC 's, have the highest speed compared to other ADC architectures [1] . As illustrated in Figure 10 , a Flash the reference value is greater than or equals the input voltage. The thermometric code is converted into a digital word by using a corresponding encoder.

Design considerations and implications
The Flash architecture has the advantage of being very fast, because the conversion occurs in a single ADC cycle. The advantage of having high speed is counterbalanced by the requirement of large number of comparators that need to be carefully matched and properly biased to ensure that the results are linear [2] . Since the number of comparators needed for an n-bit resolution ADC is equal to (2N -1), limits of physical integration and input loading keep the maximum resolution fairly low. For example, a 16-bit ADC would require 65 ,535 comparato1"; hence Flash ADC's have traditionally been limited to a maximum of 8-bit resolution with conversion speeds of 10 -40 Ms/s using CMOS technology [2].

Pipelined ADCs
The Pipelined Converter is an improvement on the Subranging Converter as it divides the conversion task into several consecutive stages. As illustrated in onto the next stage in the pipeline to be sampled and converted as it was in the first stage. This process is repeated through as many stages as are necessary to achieve the desired resolution . In principle, a pipelined converter with 'p' pipeline stages, each with an m-bit Flash Converter, can produce a high speed ADC with a resolution of N = p x m bits using p x ( 2m -1 ) comparators. For example, a two stage pipelined converter with 8-bit resolution requires 30 comparators.

Design Consideration and Implications
Pipelined Converters achieve higher resolutions when compared to the Subranging Converters and the Flash Converters containing a similar number of comparators.
This comes with a price of increasing the total conversion time from one cycle to 'p' cycles. But since each stage samples and hold its input , 'p' conversions can be underway simultaneously. The total throughput can therefore be equal to the throughput of a Flash or a Subranging Converter, i.e., one conversion 20 per cycle. The difference is that for the Pipelined Converter, the Latency is 'p' cycles [1]. Another limitation of the Pipelined architecture is that the conversion process generally requires a clock with fixed period. Converting rapidly varying non-periodic signals on a traditional Pipelined Converter can be difficult because the Pipeline typically runs at a periodic rate. counter. Figure 13 illustrates the basic block diagram of a Dual-Slope ADC.

Integrating ADCs
Dual-Slope refers to this converter since it performs its conversion in two phases.
In phase I, the integration is performed on the input signal and in phase II, the integration is performed on the reference signal. The input voltage in this case is assumed to be negative, so that the output of the inverting integrator results in a positive slope during the first integration. Figure 14 illustrates the behavior of the Dual-Slop Converter. The first integration is of fixed length, which is decided by the counter. The sampled signal produces a varying slope. After the counter is reset , the reference voltage is connected to the input of the integrator. The inverting integrator output will start to discharge down to zero at a constant slope as the input is negative with respect to the reference voltage. The counter again counts the time taken by the integrator to discharge. The final count is equal to digital value of the input. 22

Design Consideration and Implications
Integrating ADC's are used in high resolution applications but have relatively slow conversions. These Converters have comparatively low offset and gain errors in addition to being highly linear. Another advantage of these Converters is that they have a simple circuit implementation and occupy little silicon area. They are very inexpensive to produce and are commonly used in slow-moving and low cost applications like voltage and current meter displays [2]. Flash architecture. While a Flash ADC uses many comparators to convert in a single cycle; an SAR converter, as shown in Figure 15 , conceptually uses a single comparator over many cycles to make its conversion. The SAR converter basically performs a binary search through all possible quantization levels before converging on the final digital output. To elaborate its operation, in the first cycle, the Most Significant Bit (MSB) ,b 1 , is determined. In the second cycle, the next bit, b2 , is determined followed by the remaining bits until the N bits of the ADC are determined. Thus, a straight forward implementation application of an SAR ADC requires N clock cycles to complete the conversion.

Design Consideration and Implications
An SAR converter can use a single converter to realize a high resolution ADC, but requires N comparison cycles to achieve N-bit resolution, compared to 'p' cycles for a Pipelined Converter and one cycle for a Flash Converter. SAR Converters have a relatively simple design and are generally used for low speed and higher resolution applications. SAR converters are also well suited for applications that have non-periodic inputs, since conversions can be started at will. This feature Sigma-Delta Converters fall under the Oversampling Converters. As already mentioned , these converters are sampled at sampling rates much higher than the Nyquist rate. In its basic form, a Sigma-Delta Converter consists of an Integrator, a Comparator, and a single bit DAC as illustrated in Figure 16. The output of the DAC is subtracted from the input signal. The resulting signal is then integrated, and the integrator output voltage is converted to a single-bit digital output (1 or 0) by the comparator. The resulting bit becomes the input to the DAC, and the DAC 's output is subtracted from the ADC input signal. This closed-loop process is carried out at a very high "Oversampled" rate. The digital data coming 24 from the ADC is a stream of "ones" and "zeros," and the value of the signal is proportional to the density of digital "ones" coming from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output.

Design Consideration and Implications
One of the most advantageous features of Sigma-Delta architecture is the capability of noise shaping, a phenomenon by which much of the low-frequency noise is effectively pushed up to higher frequencies and out of the band of interest [2]. ' As a result , the Sigma-Delta architecture has been very popular for designing low-bandwidth high-resolution ADCs for precision measurement.
Another advantage is that , since the input is oversampled, the requirement of anti-alias filtering is greatly relaxed [1] . A limitation of this architecture is its latency. The latency is caused by the digital filter and is substantially greater than that of the other architectures.  They are also known to have good resolution. Sigma-Delta's that fall under oversampling converter architecture have a very good resolution at reasonably high speeds. Thus, depending on the application a particular architecture is a "best choice" specific to that application and as discussed in the previous section, every architecture has its own advantages and trade-offs. Hence the designer depending upon the application, selects the most suitable architecture for that particular design.

Successive Approximation ADC
Successive Approximation ADC employs a "binary search" algorithm in a feedback loop to determine the closest digital word to match an input signal.
As illustrated in the Figure 15 Design Considerations: Although, this architecture is an improvement on the conventional binary weighted resistor DAC, it still suffers from few disadvantages.
The Integral and Differential Non-Linearity errors are introduced from the mismatches in the resistors comprising the ladder [2].
• The finite 'ON' resistance of the switches add to the resistance of the ladder network. The switch 'ON' resistance must be much less than the resistance of the resistors comprising the ladder to maintain high accuracy.
• Another drawback of this circuit is that the currents flowing through the switches vary widely.

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• The minimum size of the smallest capacitor is often dictated by uniformity and matching considerations. Hence, the area and the capacitance of large arrays are huge and this results in an enormous input capacitance for the converter, which in turn slows down the preceding circuit.
• The Layout gets complicated due to the large capacitor array.
• The large capacitance of the array draws large current spikes from the Ground and VreJ lines during transients, causing ringing and long settling times in the presence of inductance in series with these lines [1].

• Charge Division by 2 circuit:
This architecture overcomes few of the drawbacks of the Charge redistribution architecture. The proposed Divide by 2 circuit, as the name goes, divides the charge into half the original charge every clock cycle. This operation is repeated over for N consecutive cycles, where N is the resolution. Figure 21 illustrates the Divide by 2 circuit implementation. The circuit is realized using a Switched Capacitor implementation. The operation of the circuit is explained in detail below: • Phase I: In this phase, switches la and 1 are closed as illustrated in the figure . During this phase, the first capacitor, C, gets charged to VreJ, while the Op-amp is being reset to its threshold by closing the switch la.
• Phase II: During this phase the switches 2 and 3a are closed. In this phase, the Op-amp is taken off the reset mode and the charge across the first Capacitor C, i.e. VreJ, appears at the output of the Op-amp while the second Capacitor is being discharged to ground.
• Phase Ill: During this phase the switches lb, 1 and 3a are closed. In this ph3.fie, both capacitors fall parallel to each other. As they have the same Capacitance C across them, the total capacitance is equivalent to 2C based on the rule of equivalent capacitance across parallel capacitors. Thus the total charge across the equivalent capacitance divided by 2, which appears at the output of the Op-amp.
Phases II and III are repeated consecutively for N cycles, where N is the resolution of the ADC. The second charge is due to the overlap capacitance between the gate and the junctions. The former error usually dominates unless VeeJ is very small.
The simplest way to make the error due to charge injection small is to use large capacitors, but large capacitors require a large silicon area. An effective way to minimize this error is to use fully differential design techniques, but the tradeoff in using differential circuits is the increase in the complexity of design.

Control Circuitry and Generation of Timing Signals
In this section the control circuitry required for the functioning of the proposed ADC architecture is presented. As already mentioned in the preceding section, nonoverlapping nature of the clocks is very critical for the functioning of the switched capacitor circuits. These clocks determine when charge transfers occur and they must be non-overlapping in order to guarantee charge is not inadvertently lost.
The term non-overlapping clocks refers to two logic signals running at the same frequency and arranged in such a way that at no time both signals are high as illustrated in the Figure  • Implementation of the switches: CMOS switches are implemented. The advantage of CMOS transmission gates over the conventional NMOS switches is that they have less ON-resistance. The settling behavior of the switched capacitor depends on the total capacitance and the ON-resistance of the switches, T =CL* RoN, thus CMOS implementation helps in having a better op-amp settling behavior. In addition to the lesser ON-resistance, they allow a wider swing of the signals and the error introduced because of the charge injection is less in the CMOS implementation when compared to the NMOS implementation.
• Charge Injection Error: The MOS switches exhibit channel charge injection and clock feedthrough. When the MOS is ON, a certain amount of charge is present in its channel. When the MOS is turned off, the principle of charge conservation dictates that this channel charge gets redistributed and ' accumulates in the source and drain terminals. This introduces an error in the sampling capacitor, which is also referred as the clock-feedthrough. Use of large capacitors reduces the error due to charge injection. The effect of larger capacitors will be discussed in the next point.
• Size of the Capacitors: As already mentioned, the error due to charge injection is minimized by using larger capacitors but this is counter-balanced by increase in the total capacitance of the circuit which again has an impact total performance of the op-amp. Use of larger capacitance also increases the silicon area. Hence the size of the capacitors used has to be optimized, so that the performance of the accumulator is not affected. The size of the capacitors implemented for the proposed design is 0.8 pF, taking into account the above design considerations.
• Op-amp offset voltage: Finally the error introduced due to inherent op-amp offset voltage has to taken into consideration. This error at the end of the N iterations is given by Where Vos is the offset voltage of the Op-amp. This error can be minimized by implementing an extra capacitance in series with the negative input terminal of the op-amp. This capacitor then gets charged to Vos, the offset voltage of the op-amp and thus cancels it out.
From the above design consideration, it can be concluded that use of larger ( w /1) ratio for the switches lowers the RoN of the switches and thus improves the settling behavior of the op-amp, but increases the error due to the clock-feedthrough as larger switches accumulate larger channel charges.
Hence there is a trade-off in selecting the (w/1) ratio of switches. For the propbsed design the size of switches implemented is (9/2).

Divide by 2 circuit
The Figure 29 illustrates the Divide by 2 circuit implementation. As the functionality of the divide by 2 circuit has already been in Chapter 3, it will not be dealt here to avoid redundancy. As the figure illustrates, a switched capacitor implementation is used for the design of the divide by 2 circuit also. Hence all the design considerations, discussed in case of the accumulator section, apply here. Thus, taking the various design consideration into account , the sizes of the capacitors and the switches realized is 0.8 pF and (w/1) = (9/2) respectively. The precise matching of the capacitors is very critical to achieve an accurate division of charge. Hence the error introduced due to improper matching of the capacitors should be taken into account. If it is assumed that the capacitors are matched with an error t:, then the total error introduced can be calculated as follows. Repeating the above calculation of N cycles, where N is the resolution, we get the error introduced due to mismatching is given by ( ~;/) * (1 -Jf E).
The ways of minimizing the mismatch errors in the capacitor layout are discussed in Chapter 5 under layout considerations. Figure 30 illustrates the simulation results of the divide by 2 circuit and the accumulator implemented. Where Casis the gate capacitance of the preceding circuitry. In case of the divide by 2 circuitry, as illustrated in Figure 28 , as the circuit operates in 3 phases as discussed in chapter 3, the load capacitance is phase 2 and phase 3 is given by C 2 /2 and 3C/2 respectively. Considering the worst case scenario, the load capacitance at the output of the op-amp is given by

Output Registers
The Digital equivalent of the Analog input, which is the output of the comparator are latched using Flip-flop's and latches.

CHAPTER 5 Layout and Simulation Results
In this chapter, the initial Floor-planning of the circuit and the various precaut ions t aken while doing the layout to achieve good performance are discussed .
Finally the simulation results of the complete SAR ADC are presented.

Layout Considerations
In the design of mixed signal circuits, several important layout issues should be considerM to realize high-quality circuits. Important points to be considered when laying mixed-signal circuits are device matching and noise. Effects of device matching and noise can be reasonably reduced, if proper precautions are taken while laying out the circuit. As a good practice, a well is placed under the clock lines as a shield. The shields placed under the analog core and the digital core are also isolated by connecting them to different rails as the shield near the control signals could pick up clock noise. As will be discussed in the next section, different power supply lines are used for both digital and analog parts.

Noise Considerations
One crucial issue to be considered in mixed-signal layout is noise. Noise injected into the micro-circuit can be broadly divided into supply-rails noise and substrate noise. Digital circuits inject noise into the surrounding substrate as well as digital power supply rails whenever they change states. To avoid supply noise, it is critical to have different power-supply rails for analog circuits and the digital circuits, which can inject large spikes in the analog power rails. It is a good practice to connect these rails only off the chip. Also, care must be taken to separate the analog interconnects from the digital interconnects as they do not have zero impedance. To minimize the effects of substrate noise, guard rings and wells are placed around the digital and analog parts to create isolation. These help to avoid 57 the substrate noise from propagating through the resistive substrate. N-wells are used to isolate substrate noise because the doping on the wafer surface is P-type.
Additionally, n-well's act as a bypass capacitor and help in lowering the noise on the VDD rails. Finally, after finishing the layout , the unused space must be filled with additional contacts to both the substrate and to the wells which act as the by-pass capacitors as already mentioned.

Matching Issues
The effective sizes of the microcircuit components cannot be accurately determined due to a variety of two-dimensional effects introduced during the fabrication.

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The inaccuracies thus introduced effect the ratio of sizes. This error can be minimized by realizing larger components from a number of unit sized components.
Although this approach increased the area, it is usually preferred for the accuracy.
As already discussed in the chapter 3 and chapter 4, for the proper functioning of the SAR ADC , precise matching of the capacitors is required. The main sources of errors in realizing capacitors are due to over-etching and oxide thickness gradient across the surface of the microcircuit. The gradient error is minimized by realizing the capacitors by using the common-centroid layout as illustrated in the Figure 36.
This realization helps in canceling the gradient effects in both the x and the y directions and thus minimizing the gradient errors. As the number of capacitors required in implementing SAR ADC is less , common centroid implementation is not required as the oxide-thickness variations are reasonably less in a small area. =· · · · · · · · · · · · -· -· · · . !  to a Computer and processed using mathematical tools like MATLAB. One test methodology, to verify the dynamic or spectral characteristics of an ADC is the Fast Fourier Transform (FFT) test [2]. This test can be performed by using signal processing tool-kit in MATLAB, which performs the FFT on the output captured in the LSA. This allows us to calculate the Signal to oise ratio (SNR) of the ADC , which is evaluates the performance of the ADC. Figure 42 illustrates the FFT results of the data captured from the test chip.  · · ·· · · · · · Vref= 4· .s4v