A Comparison of Tripolar Concentric Ring Electrodes to Disc Electrodes and an EEG Real-Time Seizure Detector Design

The electroencephalogram (EEG) is broadly used for research of brain activities and diagnosis of brain diseases and disorders. Although the EEG provides good temporal resolution, millisecond or less, it does not provide very good spatial resolution. There are two main reasons for the poor spatial resolution, (1) the blurring effects of the head volume conductor, and (2) poor signal to noise ratio. The surface Laplacian of the potential distribution was found to increase the spatial resolution. Several potential interpolation based methods were previously developed to estimate the surface Laplacian. However, these methods are generally complicated in terms of computation, which limits their real-time applications. Previously a special electrode, the tripolar concentric ring electrode (TCRE), was developed and proven to be a much simpler approach to estimate the surface Laplacian while achieving significantly better signal to noise ratio and approximation to the surface Laplacian. In the first part of the dissertation work, computer simulations comparing spatial resolution between conventional EEG disc electrode sensors and TCRE Laplacian sensors were performed. For verification of the computer simulations visual evoked stimulus experiments were performed to acquire visual evoked potentials (VEPs) from healthy human subjects. Analysis of the computer simulation results shows that the TCRE Laplacian sensors can provide approximately a ten-fold improvement in spatial resolution and pass signals from specific volumes. Placing TCRE sensors near the brain region of interest should allow passage of the wanted signals and reject distant interference signals. It was also shown that the TCRE VEPs appeared to separate sources better than disc electrode VEPs. In the second part, a tripolar EEG based automatic seizure detection algorithm was developed for rats, the paramters of the detector was optimized based on the recorded data. According to this algorithm, a Matlab based real-time detector was implimented and tested. In the last part of the dissertation, a prototype of FPGA based automatic seizure detector was Described, which has the ability to detect signal from many more channels real-time. An multichannel EEG monitor system was also described.


ABSTRACT
The electroencephalogram (EEG) is broadly used for research of brain activities and diagnosis of brain diseases and disorders. Although the EEG provides good temporal resolution, millisecond or less, it does not provide very good spatial resolution. There are two main reasons for the poor spatial resolution, (1) the blurring effects of the head volume conductor, and (2) poor signal to noise ratio. The surface Laplacian of the potential distribution was found to increase the spatial resolution. Several potential interpolation based methods were previously developed to estimate the surface Laplacian. However, these methods are generally complicated in terms of computation, which limits their real-time applications. Previously a special electrode, the tripolar concentric ring electrode (TCRE), was developed and proven to be a much simpler approach to estimate the surface Laplacian while achieving significantly better signal to noise ratio and approximation to the surface Laplacian. In the first part of the dissertation work, computer simulations comparing spatial resolution between conventional EEG disc electrode sensors and TCRE Laplacian sensors were performed. For verification of the computer simulations visual evoked stimulus experiments were performed to acquire visual evoked potentials (VEPs) from healthy human subjects. Analysis of the computer simulation results shows that the TCRE Laplacian sensors can provide approximately a ten-fold improvement in spatial resolution and pass signals from specific volumes. Placing TCRE sensors near the brain region of interest should allow passage of the wanted signals and reject distant interference signals. It was also shown that the TCRE VEPs appeared to separate sources better than disc electrode VEPs. In the second part, a tripolar EEG based automatic seizure detection algorithm was developed for rats, the paramters of the detector was optimized based on the recorded data. According to this algorithm, a Matlab based real-time detector was implimented and tested. In the last part of the dissertation, a prototype of FPGA based automatic seizure detector was Described, which has the ability to detect signal from many more channels real-time. An multichannel EEG monitor system was also described.    Electroencephalography (EEG) measures voltages from the neural activity of the brain. As a noninvasive method with high temporal resolution, EEG has clinical benefits in the diagnosis of brain related diseases and is useful in research. However, EEG suffers from poor spatial resolution due to the blurring effects primarily from different conductivities of the volume conductor [1].
To improve the spatial resolution the surface Laplacian, which is the second spatial derivative of the potential distribution on a surface, has been applied to EEG [1,2]. The surface Laplacian is a high pass spatial filter, which sharpens the blurred potential distribution on the surface [2] and produces an image proportional to the cortical potentials.
There are generally two approaches to obtain the surface Laplacian. The first approach, referred to as the global surface Laplacian, is based on the construction of the potential interpolation equations on the surface [3]. The potentials from conventional disc electrodes have been utilized for the interpolation approach. The second derivative of the interpolation equations gives the global surface Laplacian.
One of the major advantages of the global surface Laplacian is that it can encompass all points on the surface with a limited number of electrodes. A drawback of the global surface Laplacian is that the second derivative applied to the potential interpolation equations may not always be a valid estimate of the surface Lapclacian, it may produce distorted results [4,5,6,7].
The second approach is the local surface Laplacian. Instead of applying the derivative to the global interpolation equations, the local surface Laplacian method approximates the surface Laplacian based on potentials from nearby electrodes. A typical example is Hjorth's [8] five point method, where the local surface Laplacian is obtained by calculating the difference of the potential on the electrode and the average potential on its neighboring four electrodes. The local surface Laplacian method does not rely on the second derivative of the interpolation equations, but it also has some drawbacks: 1) when the nearby electrodes are too far away, which is usually the case with the 10-20 system configuration, the resulting local surface Laplacian might not be a good approximation of the surface Laplacian [6], 2) the local surface Laplacian can only be estimated on the locations of electrodes but not from the edge electrodes.
Although conventional disc electrodes could be used for this approach, there would still be the same limitations present such as poor spatial resolution and signal to noise ratio.
Previously Besio et al. developed a new EEG electrode structure, the tripolar concentric ring electrode (TCRE) [9]. The TCRE is made up of two concentric metal rings and a metal central disc layout on a flat printed circuit board (PCB). Both a conventional electrode and TCRE are shown in Figure 1. Due to this special structure, a linear combination of the potential from the three elements of TCREs directly forms the local surface Laplacian of the potential distribution [9]. We compared the TCREs with the conventional disc electrodes in both computer simulations and real EEG 3 recordings. The results show that the TCREs are superior to conventional EEG electrodes on the surface Lapalcian estimation and spatial resolution.

Epilepsy Seizure Detection
Epilepsy affects about 50 million people worldwide, and nearly 80% of them are living in developing countries. Anti-epileptic drugs have been successfully used to treat some patients. According to recent studies, up to 70% of the newly diagnosed children and adults with epilepsy can be successfully treated with anti-epileptic drugs.
However, this implies that these drugs are not effective in about 30% of the patients.
In addition, the side effects of these drugs may reduce the quality of life of the patients.
Surgery is another approach employed for epilepsy treatment, but it includes risks.
Moreover, due to the relatively high cost of the two approaches above, about 75% of the patients in developing countries may not even receive treatment [10].
As a possible alternative, physical stimulation approaches have been gaining interest. Among these approaches, the implantable electrical stimulation approaches such as vagus nerve stimulation (VNS) [11], deep brain stimulation (DBS) [12] and responsive neurostimulation (RNS) [13], have been widely studied recently. Moreover, the VNS has even been approved by FDA in 2005 as a treatment for medicationresistant depression. Meanwhile, noninvasive stimulation methods have also been developed, such as transcranial direct current stimulation (tDCS) [14], and repetitive transcranial magnetic stimulation (rTMS) [15].
Detection of epilepsy is a necessary stage prior to epilepsy treatment. was defined by Gloor [18] as a triangle wave that is distinguished from the background signal, and has an amplitude at least twice that of the previous 5s of background activities of any EEG channel, and with a duration of at most 200 ms.
Algorithms such as mimetic, linear predictive and neural networks [19] are mostly employed for spike detection for epilepsy. For the frequency domain, most works focused on detecting specific features related to seizures. Fast Fourier transform [20], time-frequency analysis [21], wavelet transforms [22], and nonlinear based analysis [23] are the most used methods.
Through the use of the high quality EEG signals recorded with TCREs, we developed a real-time automatic seizure detection algorithm based on the cumulative sum (CUSUM) detector [24]. The parameters of the detector were optimized by analyzing the recorded data from previous animal experiments. Due to the special structure, the TCREs have also shown the ability to perform focal electrical stimulations. Unlike the normal electrical stimulation via conventional disc electrodes that is usually applied across the head, the electrical stimulation via a TCRE is conducted between the outer ring and the central disc. Therefore, the stimulation current is focused on a small volume right underneath the TCRE. This type of electrical stimulations is called transcranial focal electrical stimulation (TFS).
Previously we have reported the promising experiments applying TFS on rats, the results showed that TFS significantly reduced the highly synchronized brain activity within the beta and gamma bands at the early stages of PTZ-induced seizure development, also the number of rats survived after TFS significantly increased [25].
The combination of TCREs, automatic seizure detector, and TFS forms a closed loop seizure controller.
We also implemented the real-time seizure detector with automatic TFS triggering based on a laptop personal computer running our Matlab software control algorithm for a small number of channels [26]. Animal experiments were performed to verifying this detector.

Hardware Implementation of the Seizure Detector
We showed that the personal computer and Matlab based automatic seizure detector is suitable for rats [26]. But our ultimate goal is to develop an automatic seizure detector and controller for humans. The common EEG recording system for humans can be 20, 32, 64 or even 128 channels. Threfore, the seizure detector needs to have the ability to process the data from 20 or more channels. For practicality, we want the detector to be portable, so that patients can carry it with them. To meet these requirements above, we developed a field programmable gate array (FPGA) based embedded EEG recording and signal processing system which can be used as an automatic seizure detection system. Also, we further extended the design with a USB interface and the driver and application software in a PC to form a complete EEG recording system.

EEG recording system
The first human EEG signal was recorded by German physiologist and psychiatrist Hans Berger in 1924 using a galvanometer [27]. Albert Grass built the first commercial EEG systems, called Grass Model 1 in 1935 [27]. concentric inhomogeneous spherical head model [28]. In the comparison, the global surface Laplacian estimation is based on the spherical spline interpolation method introduced by Perrin [3], while the local surface Laplacian estimation is based on the TCRE Laplacian algorithm [9]. Noise is added to the simulations to make the results more realistic.

Local Surface Laplacian Estimation Based On TCRE
The TCRE is shown in Figure 2. The electrode is made of three elements: outer ring, middle ring, and the central disc. The tripolar Laplacian is given by the combination of the potentials from the three elements of the TCRE [9]: In equation (2.1), d V denotes the potential from the central disc, m V denotes the potential from the middle ring, o V denotes the potential from the outer ring and R is the radius of the middle ring.

Figure 2 Tripolar concentric ring electrode (TCRE) sensor
In the real TCRE EEG recording (tEEG), a TCRE is connected to two amplifier channels: the disc is connected to the negative inputs of both channels, the middle ring and outer ring are connected to the positive inputs and then the signals are amplified and digitized and combined as in equation (

Interpolation
The spherical spline interpolation method was introduced by Perrin et al. [3].
Perrin models the head as the surface of a sphere, which is not exactly the same as the shape of the human head, but approximates the head for comparison. The spherical model is commonly used in both research and clinical situations [29] The surface Laplacian operator in the spherical coordinates system is defined as: Applying equation (2.6) to equation (2.2) gives the surface Laplacian of the spherical interpolation: ( ) ( )  (2.7) The truncated singular value decomposition method was applied to solve the inverse problem of the ill-posed matrix in equations (2.4) and (2.5) [30].

The Four-layer Spherical Head Model and the Analytical Surface
Laplacian Figure 3 shows a four-layer concentric inhomogeneous spherical model [28] to represent the human head. The four layers represent brain, cerebrospinal fluid, skull, and scalp. The corresponding radii of the layers are: 7.9cm, 8.1cm, 8.5cm and 8.8cm; the conductivities of the layers are: 3.3×10 -3 S/cm, 10.0×10 -3 S/cm, 3.3×10 -3 S/cm, 4.2×10 -5 S/cm, 3.3×10 -3 S/cm, respectively. Current dipoles, described later, are employed to model the brain activity. The potentials on the surface of the model due to a current dipole located at the z axis inside the brain pointing to x, y, z directions are given by the following equations [28]:

Computer Simulation Methods
The computer simulation was conducted to compare the global spline surface Laplacian and the local TCRE surface Laplacian to the analytical Laplacian. To model the activities of the brain cortex area, ten dipoles with eccentricities of around 0.89 were utilized, which are listed in Table 1. The locations of the dipoles were modeled in the visual cortex area of the brain to compare the simulation results to those of actual visual evoked potential (VEP) recording experiments that we conducted. The moments of the first five dipoles had a radial direction, and the remaining five dipoles were at the same locations, but with a tangential direction. Table 1 lists all of the ten dipoles. In each simulation, one of the dipoles listed was selected as the signal source. To simulate the potential recorded on the elements of the TCREs, we assume that there are 'sampling points' uniformly distributed on the surface of the electrode elements. The potential of all "sample points" on each specific element was calculated and the average of all the sample points for each specific element was considered the potential for that specific element of the TCREs. To determine the number of 'sampling points' necessary for stable calculations we examined the effect of the 'sampling points' density on the averaged potential. The higher the density of uniformly distributed 'sampling points', the closer the averaged potential is to the real potential. In our initial analysis we incrementally increased the density of 'sampling points' on the TCRE and compared the averaged potential. When the difference in potential due to adding more points was less than 0.1 percent we stopped adding 'sampling points'. For the conventional disc electrodes, we assumed its diameter was the same with that of the outer ring of the TCREs. We used the same process to find the 'sampling points', for the conventional disc electrode.
Three different noise conditions and four different electrodes configurations were considered in the simulation. The noise conditions were: (1) no additive noise, (2) with white Gaussian noise, and (3) with dipole noise (simulating brain activity not considered the brain source of interest). An environment without noise is not practical, but this study is still valuable as a base to reveal the effect of different types of noise to the surface Laplacian estimation methods. White Gaussian noise (WGN) was employed to simulate the noise from the environment and EEG recording equipment.
For the conventional disc electrode, 20% WGN was added to the calculated potential on each electrode; for TCREs, 20% of the WGN was added separately to , since they physically are amplified with two separate circuits, as described in the previous section. The WGN level is defined as the ratio of the standard deviation of WGN and the standard deviation of the potential, to which the noise is added, over all the electrodes [31]. Moreover, the brain activity interference from the deep part of the brain was modeled as a noise dipole with eccentricity around 0.85. The four electrodes configurations are: (1) 19-electrodes, (2) 32-electrodes, (3) 64-electrodes, and (4) 128-electrodes. The 19-electrodes were placed at the standard 10-20 system locations. The 32-electrodes, 64-electrodes, and 128-electrodes locations were selected from the 5-5 system [32]. The global spline surface Laplacian and the local TCRE surface Laplacian were calculated at the locations of the electrodes and then compared to the analytical surface Laplacian using the correlation coefficient.
All the statistical analysis was performed using Design-Expert software (Stat-Ease Inc., Minneapolis, MN, USA). Full factorial design of analysis of variance (ANOVA) was used with four categorical factors [33]. The first factor (A) was the type of the electrode presented at two levels corresponding to conventional disc electrodes and tripolar concentric ring electrodes. The second factor (B) was the number of electrodes presented at four levels corresponding to 19, 32, 64, and 128 electrodes. The third factor (C) was the presence and type of noise presented at four levels corresponding to no noise, presence of white Gaussian noise (WGN), presence of a noise dipole, and presence of both WGN and the noise dipole. Finally, the fourth factor (D) was the dipole location presented at ten levels corresponding to 10 signal dipole locations from Table 1. The response variable was the correlation coefficient of the simulated surface Laplacian and the analytical surface Laplacian calculated for each of the 2*4*4*10 = 320 combinations of levels of four factors.

Computer Simulation Results
The correlation coefficients of the TCRE surface Laplacian and disc spline Laplacian to analytical surface Laplacian without any added noise are listed in Table 2.
The averaged value and the standard deviation of the correlation coefficient in each column are listed at the third and second rows from the bottom of the table respectively. Table 3 lists the correlation coefficient of the TCRE surface Laplacian and disc spline Laplacian to analytical surface Laplacian with 20 percent WGN added. Table 4 shows the correlation coefficient of the TCRE surface Laplacian and disc spline Laplacian to the analytical surface Laplacian with the presence of a noise dipole.
As we mentioned above, the electrical activity in the deeper brain was considered as another type of noise. This type of noise was also modeled as dipoles, but with smaller eccentricities, which means the brain source of the dipole is closer to the center of the head. In every simulation performed with this type of noise, a noise dipole with unit moment was randomly selected with the eccentricity of approximately 0.85.
In the last set of simulations, we considered both the 20 percent WGN and the noise dipoles and the results are listed in Table 5. Table 5 shows our most realistic simulation results. Correlation coefficient data obtained in this simulation for 320 combinations of factor levels is summarized in Table 6 (averaged for ten dipole locations).
The full factorial design of our study is presented in Table 6. We used the Box-Cox procedure to select the optimal power transformation improving the spread of studentized residuals [33].   Table 4 Correlation coefficient with the presence of brain dipole noise Table 5 Correlation coefficient with the presence of white Gaussian noise and dipole noise

Visual Evoked Surface Potential (VEP) Recording Experiment Setup
We recorded from 15 selected locations on the scalp over the occipital lobe visual cortex area from the standard 10-5 system with the TCREs, the locattions of the electrodes are shown in Table 7. A reference electrode and a ground electrode were placed on the forehead of the subjects. Before the recording, the scalp was first abraided with Nuprep, a mild abrasive cleanser, and then Ten-20 electrode paste was used to match impedances between the TCRE and the scalp. The impedances were measured and any TCREs with impedances above 5 Kohms were attached again. The TCREs were connected to the preamplifiers we developed, A Grass Technologies The analysis of the recorded EEG signals varied depending on the type of signals recorded. We used the outer ring of the TCRE as a disc electrode emulation (eEEG). Recorded data was segmented with the peaks of the LED control pulses. We utilized about 200 segments for every subject. The first 150 ms of data for each segement was then ensemble averaged to obtain the visual evoked potential (VEP).

Visual Evoked Surface Potential (VEP) Recording Experiment Results
From Figure 4 we can see that the TCRE Laplacian sensor was able to separate VEP sources. In Figure 4A, of the spline Laplacian map from disc electrodes, in the top central area there is a red and orange area (marked with an arrow). In the same area of Figure 4B we can see the TCRE Laplacian sensor map shows that there were two distinct sources. Panel C and D of Figure 4 shows the normalized grand-averaged EEG VEPs and tEEG VEPs that these maps were made with. From Figure 4C and D we can see that there is a positive going wave at approximately 100 ms after the photic stimulation pulse.

Disscusion of the Spatial Resolution Comparison
The computer simulation results show that with an increase in the number of electrodes, the spline surface Laplacian estimation has also been improved, while the TCRE surface Laplacian is not sensitive to the number of electrodes. The spline surface Laplacian estimation relies on the potential recorded on every electrode to optimize the interpolation parameters, therefore the more sensors leads to a better estimation of the parameters. On the other hand, each TCRE measures the surface Laplacian independently, as a result, the tripolar surface Laplacian does not rely on the number of sensors. After comparing the correlation coefficients in Table 2, it is apparent that at least up to 128 sensors, the tripolar surface Laplacian still outperforms the spline surface Laplacian.
The comparison of Table 2 and Table 3  The results also indicate that the spline interpolation algorithm is more sensitive to random noise compared to the TCRE Laplacian algorithm. Table 4 shows the results with the presence of the deep brain activity noise, which was also modeled as dipoles with smaller eccentricities. Both the spline surface Laplacian and TCRE surface Laplacian were affected by brain source dipole noise. what areas of the brain the signals should be coming from and those sensors could be preferentially treated while other locations could be less important.
In the last computer simulation, both 20 percent WGN and the dipole noise were added and the results are presented in Table 5. This simulation is the most realistic of our simulations. The results shown in Table 5 suggest that the TCRE surface Laplacian has at least two significant advantages compared to the spline surface Laplacian. First, the TCRE surface Laplacian works nearly the same with different numbers of electrodes (from 19 electrodes to 128 electrodes); second, the TCRE surface Laplacian is stable to different noise dipoles, which is due to its small half sensitivity volume (HSV), or, in other words, local recording characteristic.
In the simulation, the eccentricities of signal dipoles were set at around 0.9. This eccentricity was used since we were mainly interested in the visual cortex area of the brain. In a previous study [34], the eccentricities of the dipoles were usually set at 0.85 or smaller. We want to mention that the eccentricity of the dipole has considerable impact to the Laplacian estimation. Generally, the smaller the eccentricities the better performance of the spline and tripolar Laplacian estimation. In addition, the relative location of the dipole to the sensors is also an important factor regarding the Laplacian estimation. We observed in the simulation that if the dipole was close enough to one of the sensors, there would be a large difference between the analytical and the estimated Laplacian. This holds for both spline and the tipolar surface Laplacian estimation.
The VEP experiments showed that we can acquire VEP signals from humans.
Beyond the acquisition we were able to see separate sources in the TCRE Laplacian maps that were not separated in the spline Laplacian maps, which is shown in Figure 4.
It should be noted that we are not certain where the sources are in the visual cortex however, Fig. 4A and B are indicative of the other subjects as well.

Conclusion
From the computer simulations there is a significant improvement in estimation of the Laplacian using TCRE Laplacian sensors compared to disc electrodes and the spline Laplacian. The human experiments verified that we can record VEP signals using TCREs and that the tEEG signals showed two sources while the EEG signals showed only one source. control seizures in rats [25]. However, we waited until we observed the first strong behavioral change elicited from the convulsants, a myoclonic jerk (MJ), before we turned the TFS on manually. Observing our electrographic data from rats before and during seizures we hypothesized that the tEEG signal could be used to automatically trigger the TFS to control seizures. In reality we do not want to develop an automatic seizure control system for rats but took this opportunity to prove that a seizure warning, and or control, system could be developed utilizing the TCRE and TFS technologies.
In the previous chapter we introduced a unique electrode, the TCRE, and showed that the TCRE outperforms the conventional disc electrode in terms of surface Laplacian estimation. The TCRE has been proven to have several advantages compared to conventional disc EEG, such as better spatial resolution, higher signal to noise ratio, and less mutual information between nearby electrodes [35]. Due to the special structure, the TCRE also has shown the ability to perform focal electrical stimulations. Unlike the normal electrical stimulation via conventional disc electrodes that is usually applied across the head, the electrical stimulation via a TCRE is conducted between the outer ring and the central disc. Therefore, the stimulation current is focused on a small volume right underneath the TCRE. We call this type of electrical stimulations transcranial focal electrical stimulation (TFS). Beyond the focal stimulation the signal acquisition advantages suggest that the TCREs may have benefits for EEG based epileptic seizure detection. In this chapter, we present a real time automatic seizure detection system that was tested on rats.

Detector
The TCREs signals were used to monitor brain activity and when a seizure was detected the TFS was triggered. To develop an efficient detector, we analyzed the recorded TCREs EEG (tEEG) signals from 5 rats, (the details of which are given below). In the tEEG signals we found a very stable pattern in the band of 0 to 100 Hz.
The power spectral density of the seizure signals was higher than the non-seizure signal, which is shown in Figure 5. From Figure 5, the seizure and non-seizure situation is clearly separated. Figure 5 also suggests that seizures are usually accompanied by a significant change in the on-going electrical activity of the brain and therefore the power spectral change detectors are appropriate for seizure detection.
However, in some more complicated situations, the EEG signal can be corrupted with noise, which makes the determination of the seizure a challenge. To make the detector more stable in noisy situations, we independently detected the power spectral density change in several sub-bands. The 1-100 Hz bandwidth is historically divided into  if two epochs in three consecutive epoches were marked by the CUSUM detector for power change. For each sub-band of the seizure data, we applied a CUSUM detector to detect the sudden power change. Table 8 shows the optimized parameters and detection results for each sub-band. According to the table, the Delta band (0.  and Theta band (4-8Hz) were the two most reliable sub-bands as seizure indicators.
The real-time automatic seizure detection algorithm was implemented with Matlab. In the implementation, Matlab interacts with the data acquisition hardware (Measurement Computing USB-2537) through a device driver that was embedded in Matlab. For initialization, the hardware was configured to sample 6 channels at 256 SPS. In the recording, a timer callback function was triggered every second to retrieve data of 1536 samples, which is for 256 samples per channel and 6 channels, from the data acquisition hardware. Figure 8 shows a diagram of the procedure which is described below. The retrieved data was further processed by the following steps: first, the data of the two channels from the same electrode was combined according to the formula (2.1), which forms three tEEG data series; second, the Hanning window was applied to the three data series; third, FFT transform was applied to the three data series; fourth, the spectrum sub-band power was utilized to optimize the parameters of the CUSUM detector if in: the (1) baseline session, or (2) passed to the CUSUM detector for sudden change detection if in the detection session; fifth, once the seizure activity was detected, an alarm was triggered, so that we can manually applied the TFS to the rat under seizure detection. Figure 9 shows typical processed data for a TFS-treated rat. Trace #1 is the tEEG from electrode (b) in Figure 7. Traces #2 and #3 are the relative power and seizure detector output for the Delta band, respectively. Traces #4 and #5 are the relative power and seizure detector output for the Theta band. In Traces #3 and Traces #5, detection results are denoted by values '0' and '1', where '0' means no seizure was detected, '1' means seizure was detected. The two of three smoothing algorithm, which was described previously, was employed for the final detection decision. The vertical dashed line shows the time when the seizure was detected. In this experiment, the first myoclonic jerk was observed at approximately 2 minutes and 10 seconds. The averaged performance of the automatic seizure detector is listed in table 9.

Discussion
We were able to 'train' our CUSUM detector (i.e., to select the s parameters) using the control rat data and apply those parameters to test the detector on data that were not used for training (the generalization property of the CUSUM algorithm). The Much work has been performed in the field of seizure detection [36,37,38,39].
For our experiments we have a special case where we know when the convulsant is given after a baseline period. We do not need to resolve long periods of baseline activity vs. seizure activity. For these experiments we were only interested in determining when the TCRE EEG showed increased activity due to the PTZ. We did not need to discriminate False Positives, 'seizure' during baseline, only during a short period post PTZ. The rest of the data is known 'seizure' data and therefore we only had to discriminate True Positive and False Negative (no 'seizure' during 'seizure').
Although using combinations of bands may be more robust for detection our data suggest that the Delta power in the on-going EEG may be most informative in this regard. This suggestion needs further confirmation in subsequent studies.

Conclusion
The CUSUM algorithm, in conjunction with TCRE EEG, correctly detects seizure activity from the Delta power changes in advance of the early behavioral manifestations of a seizure (such as MJs). Therefore, this algorithm can be used as a control signal to automatically trigger TFS with the goal to prevent seizure development.

Introduction
In the previous chapter we introduced a real time seizure detection algorithm for rats. We also implemented this algorithm in "real-time" with Matlab running on a Dell D630 laptop. The experiment showed that this detector works very well for the rat experiments. However, several drawbacks existed in the seizure detection system described above. First, the central processing unit usage of the laptop was reaching 100% while performing the real-time control with just three TCREs. Meeting the realtime signal processing requirements for multi-channel EEG seizure detection for humans, considering that human EEG recording typical utilizes 20, 32, 64, or even 128 channels, would be beyond the abilities of the laptop. Second, the use of the PC in the closed-loop system increases the system cost and limits the portability of the system. Third, the seizure detector generated an alarm for when to turn the TFS on but the TFS was actually turned on by a person, which introduced some delay between the seizure detection and the application of the TFS.
To overcome the disadvantages listed above, we developed a new FPGA platform to run the real-time seizure control on. This system will automatically detect the seizure activities and apply the TFS, which forms a portable closed-loop automatic seizure control system, as shown in Figure 10. Moreover, the hardware can also be used for a multi-channel human tEEG recording and real-time signal processing and display system.

Methods
The automatic seizure detector and EEG monitoring system contains several hardware and software subsystems. These subsystems include A-to-D converters (ADC), FPGA embedded controller and digital signal processor, USB interface, USB driver under Windows operating system, application software for signal display and data storing. The development of these subsystems is desribed in the following sections.

System Considerations
An EEG system records the potential on the scalp caused by the electrical activities from the brain. The EEG recordings for humans usually uses 20 to 128 channels and electrodes. A typical raw human EEG signal has an amplitude between 1μV to 10 mV, which indicates that the EEG signal is weak and has a high dynamic range. The tEEG signals are even weaker and have been reported to be hundreds of nanovolts [35]. The typical bandwidth of EEG recording is between 0.5 Hz to 70 Hz.
Recently researches have shown that there are EEG activities in higher bands, with the frequency as high as 500 Hz [40,41]. It seems that the wider band EEG signal recording and analysis will be the trend in the future. There are several other issues of EEG signals that must be accounted for, such as the high bias voltage caused by the half-cell effects. These are mainly dealt with in the analog domain by signal conditioning techniques, and not discussed here.
As we mentioned in the previous chapter, there are generally two approaches for seizure detection [16,17], one is spike analysis based on time domain EEG signals, the other is spectral analysis based on the spectral domain of the EEG signal. We employed the second approach, spectral analysis, to develop our epilepsy seizure detector. This was since our earlier work showed that the spectral analysis was more robust in noisy environments such as movement artifacts and mains interference.
These requirements forced us to perform the spectral analysis in real-time in the frequency domain and formed the basis for our new system design.
To digitize the tEEG signal with high dynamic range a high resolution ADC is desired. Having multi-channel capability of the ADC is also beneficial, since the capacity of the system is as many as 128 or even 256 channels. Thus we began work on implementing the analog front end, ADS1299, from Texas Instruments. The ADS1299 has 8 differential channels of programmable gain instrumentation amplifiers, and a 24-bit, 8-channel delta-sigma ADC, with daisy-chain port that supports cascading multiple chips as an ADC system with 128 channels or more. For automatic seizure detection, the up to 128 channels of data has to be transformed to the spectral domain in real-time. Two platforms, FPGA and graphics processing unit (GPU) are suitable for this task. However, the FPGA has more resources for communicating with other devices, such as communicating with ADC and USB interfaces. Thus, we used an FPGA as the ADS1299 controller, digital signal processing, and communication core.
We used an ALTERA DE-2 evaluation board with the Cyclone IV serial FPGA. The estimated data recording rate of the ADCs is about 13 MB per second, so the USB 2.0 interface, which provides a maximum data transferring rate over 30MB/s, fits the estimated data rate. On the PC side, a USB driver was developed for real-time data acquisition from the USB interface to save the data in a temporary buffer in the Windows kernel. The application software was developed to fetch the data from the data buffer in the Windows kernel and save the data to the hard disk and also display it on the screen. Figure 11 shows the high level structure of the system. Figure 11 System structure

Hardware Connection
The ADS1299 is an 8-channel ADC and programmable gain preamplifier. To build a data acquisition system with more than 8 channels, multiple ADS1299s need to be connected with the daisy-chain configuration [42], and then connected to the FPGA through a serial peripheral interface (SPI) port, which is shown in Figure 12.

Figure 12 Daisy-chain connection of multiple ADCs
With this connection, the analog to digitized data is available from the DOUT pin to the DAISY_IN pin, and sent out to FPGA through the DOUT pin of the first ADC, which is Device 1 in Figure 12. The timing for the data reading cycle is shown in Figure 13 [42]. Figure 13 Daisy-chain ADCs data reading timing

FPGA Logic Structure
The FPGA plays two roles in our system. First, the FPGA acquires and transmits the data from the ADS1299 to the computer for storage. On one side, it communicates with the ADCs through the SPI port. The FPGA must configure and acquire data from the ADCs and the FPGA must also pack the data according to the  Figure 14 Logic structure in ALTERA Cyclone IV FPGA

Multi-Channel FFT Processor Design
The multi-channel FFT processor is designed to transfer the recorded tEEG signal to the spectral domain. According to the seizure detection algorithm we developed, each time one second of data is recorded it is transferred to the spectral domain by the FPGA FFT algorithm. A commonly used sampling rate of the EEG recording is 250 Hz, therefore the data length of the FFT processor was set to 256. Due to the limit of the resources in the FPGA, an FFT processor needs to be applied to multiple channels.
The data width of the input stage of the FFT processor is 24-bits, which is determined by the output data width of the ADCs.
As mentioned above the FFT processor runs at a much faster clock than the clock of the data input rate. There are two reasons that make the data processing speed of the FFT processor the bottleneck of the seizure detector which is why it is run at a much faster clock rate than the other two processes. As a result, the pipeline multi-channel interleaving structure was employed to overcome these problems. There are mainly four pipeline FFT structures: radix-2 multi-path delay commutator (R2MDC), radix-2 single-path delay feedback (R2SDF), radix-4 multi-path delay commutator (R4MDC) and radix-4 single-path delay feedback (R4SDF), all are shown in Figure 15. Due to existence of the feedback loop, which complicates the pipelining of the butterfly multipliers [43], the single-path delay feedback structures are not suitable for high throughput rate FFT processors.
The radix-4 butterfly multipliers significantly reduce the number of stages of the pipeline structure, which helps to minimize the delay from the input to the output.
However, as we may see in Figure 16, the radix-4 butterfly multiplier is much more complicated than the radix-2 butterfly multiplier. This may not be a problem for very large scale integration (VLSI), but the resources in the FPGA are pre-placed and limited, so the complicated structure introduces significant routing delay, which limits the highest clock frequency on which the logic can run. For these reasons, we employed the radix-2 multi-path delay commutator structure to build the multichannel FFT processor. The interleaving method was employed to perform the FFT process on data from multiple channels. This method is implemented by making two changes on the single channel radix-2 multi-path delay commutator structure: (1) increase the number of the registers connected to the controllers by N times, and (2) change the controller blocks to reuse every parameter for N times. Figure 17 shows the structure of the interleaving radix-2 multi-path delay commutator for the N-channel FFT transform. The multipliers utilized in the butterflies are further pipelined to ensure the 80 MHz clock rate. Since we utilized the fixed-point data format in the computation, bit growth was considered to preserve the precision and avoid overflow.
However, there are two computations in the butterfly multiplier that may cause bit growth. First, the data width must grow 1 bit in the add/subtract stage of the butterfly multiplier. Second, the multiplication of the sinesoid value and the input data may cause an extra bit growth. The bit growth at , the multiplication of the sinesoid value only needs to be considered once in all the FFT stages [44]. To accommodate for the worst case bit growth, the width of the output of the first butterfly multiplier increases by 2 bits, the width of the output of all the following butterfly multipliers increase by 1 bit. The bit increasing consideration is shown in Figure 18.  Figure 16 Radix-2 (left) and Radix-4 (right) DIF butterfly multipliers Figure 17 16-point R2MDC with interleaving for N channels Figure 18 Eight stage Radix-2 FFT bit consideration Each stage of the FFT is built with a controller, a butterfly multiplier and a parameter module, as shown in Figure 19. The controller works as a router that directs the data and parameters to the input of the butterfly multiplier at the right time by controlling two shift buffers and the address signal for the parameter module. A round-back counter was implemented in the router. By setting the maximum value of of the round-back counter to N the controller can be adjusted to work for an N-channel FFT processor. The butterfly multiplier computes the multiply-add value: A BC + , where A and B are full scale complex numbers, and C is a normalized unit complex number. There are two approaches to implement the butterfly multiplier. The first approach, referred to as the CORDIC method, takes advantage of the multiplier of a full scale complex number and a normalized unit complex number, which is actually a rotation of the full scale complex number. The advantage of this approach is that it only takes bit shift and add, so it saves the hardware multiplier resource, but the complicated structure makes it hard for pipelining. The second approach, however, employs the normal multiplication and addition to implement the butterfly multiplier.
The parameters in the second approach are pre-computed and stored in the chip. This method, of course, cost more hardware multiplication resources, but the structure is straightforward. We employed the second method in our design. For each multiplier we utilized four multipliers and two adders. The multipliers were further pipelined to maximize the clock rate of the FFT processor. Figure 19 Detailed structure of an FFT Stage

CUSUM Detector Design
According to the seizure detection algorithm we developed, there are two main tasks. The initial task is started at the beginning for training the CUSUM detector on non-seizure data. In this task, the spectral data from the FFT processor is cumulatively averaged. At the end of this task, the average value is loaded for the CUSUM detector.
The second task is the seizure detection task. During the seizure detection, the CUSUM detector continuously monitors the power spectrum of the interested bands, and in real-time triggers the stimulator if specific features are detected, and updates the parameters according to the current power spectrum. The two tasks perform different procedures, and are therefore implemented with two different modules. The spectral data output from the FFT processor is pre-processed by the power spectral band selector, which basically computes the relative power of the specific bands that are determined in the training task. Since we employed the interleaving structure for the FFT processor, the power spectrum for different channels arrives at the CUSUM detector one by one. Also, we are only interested in certain band(s) of the spectrum. Therefore, a single CUSUM detector is sufficient for monitoring all the channels. In the EEG recordings, it is common to find some channels that are corrupted with artifacts; this is usually due to the bad placement of electrodes or loss of contact over time. These channels should be excluded from the detector, since the signal from these channels can mislead the detector. We implemented the "Channel Selector" module in the CUSUM detector that was used to disable the corrupted channels. This "Channel Selector" is implemented as a bit map, in which every channel has a corresponding bit. Value '1' on a bit means the data from corresponding channel would be sent to the CUSUM detector, otherwise the data from the correponding channel would be discarded. The bit map can be configured through our application software.

Software Design
Software was developed to initialize and transfer a data stream from the FPGA to the hard disk in the Laptop with a transfer rate up to 30 MB per second. There are three parts to this software: embedded firmware for the Cypress CY7C68053A USB controller, USB device driver for the Windows kernel, and application software for Windows user space. The dark blocks in Figure 21 are the three parts we developed.
In our design, the Cypress CY7C68053A USB controller was configured as a slave first-in first-out (FIFO) register module. With this configuration, the USB controller works as a pair of passive FIFOs. One transfers data from the FPGA to the PC, the other transfers data from the PC to the FPGA, as shown in Figure 22. The USB protocol is executed by the hardware implemented in the USB controller chip.
The embedded software was developed to configure the registers for the USB protocol execution during the initialization stage.
On the PC side, the USB host controller driver and the USB core driver are provided with the Windows operating system. These two drivers handle almost all the USB protocol affairs, as well as communicate with the device hardware, which is the Cypress CY7C68053A USB controller in our case. The main part we developed at the driver level is the USB device driver. As shown in Fig. 5.11, the USB device driver works as a bridge between the USB core driver and the application software. On one hand, the USB device driver continuously sends data read requests to the USB core driver, once the request is responded to, it saves the data to a buffer. On the other hand, the USB device driver implements several methods for the application software to fetch data, the USB interface information or send commands down to the FPGA.
The USB device driver is developed based on the Windows Driver Foundation (WDF). The WDF is a new driver model for the Windows operating system that is based on Windows Driver Model (WDM). In other words, the WDF framework encapsulates the WDM framework, and exposes a much more user-friendly interface for driver developers. Specifically, the WDF implements a set of default power management callback functions which deals with all the plug and play and power issues very well.
Even with the support of WDF framework, there are still two challenges for developing the USB device driver. First, the USB device driver has to read the data from the FIFO of the Cypress CY7C68053A USB controller immediately when it is available. Second, the buffer in the USB device driver is accessible for both the saving and fetching routine that run asynchronously, so a mechanism is needed to prevent the buffer from being accessed by the two routines at the same time while still maintaining the high speed data transfer. The first challenge is addressed by a mechanism called continuous reader. The idea is that we always maintain two or three data read requests so that while one request is returned with some data for processing, there is still a pending request for new data. There are several synchronization approaches, such as "Critical Section" or "Spine Lock", which can guarantee only one routine accessing the buffer at any single time by blocking the other routine that is trying to access the buffer. But simply applying these approaches will decrease the performance of the driver in terms of data transfer rate. For instance: if a data read routine for the application software obtained the access to the buffer, and started to copy data, the read completion routine has to wait for the copy procedure to finish before it can access the buffer and save the data. Therefore, we employed the circular buffer structure that stores the data in the kernel. This structure allows us to avoid the synchronization problem. Two pointers are utilized in the circular buffer, one pointer points to the start block of circular buffer, the other pointer points to the end block of the circular buffer. The read completion routine is responsible for updating the end pointer, while the read routing for the application software updates the start pointer.
The pointers round back to the minimum address of the buffer once they reach the maximum address. If the start pointer catches up to the end pointer, the buffer is empty; otherwise if the end pointer catches up to the start pointer, the buffer is full. If the end pointer further overlaps the start pointer, data in the buffer is corrupted. The overlap detector triggers an alarm to the application software about this serious problem.
However, it's the application software's responsibility to prevent the circular buffer from becoming full. The depth of the buffer is calculated according to the current sampling rate andthe number of recording channels. Three endpoints were implemented in the driver: default control endpoint, input endpoint and output endpoint, as shown in Figure 23. The control endpoint is the utilized to USB interface information retrieval. The input endpoint is employed to transfer data from the hardware to the Windows USB driver. The output endpoint is used to send data from the driver to the hardware. The structure of the driver is shown in Figure 24. Figure 23 Endpoints of the driver and thevirtual connection to the dardware As we mentioned above, our application software is responsible for retrieving the data from the USB device driver without any loss. A precise timer is desired to finish this task. Thus, we employed the timer-queue timer, which is mostly applied in the multimedia field. According to our testing on the Windows XP operation system, the timer-queue timer can give a quite constant interval of 1.1 ms with the jitter less than 0.01 ms. In our application, the timer-queue timer triggers a timer call back function every 1.1 ms to retrieve data from the buffer of the USB device driver. According to the two tasks of the applications software, the retrieved data is sent to two buffers in the user space. First, the data is sent to a ping-pong buffer. Every 30 seconds, an extra thread is created to write the data in one memory block of the ping-pong buffer to the hard disk, and in the next 30 seconds the coming data will be sent to the other memory block. Second, the data is also sent to a buffer in the signal display module. In our signal display module, data is processed and mapped to the pixels on the screen. The procedure flow chart of the application software is shown in Figure 25. The synthesis results are shown in Figure 26 and Figure 27. To give a comparison, even though it's not a fair comparison, the synthesis results of the standard single channel 256-point fixed bit-width (24-bit) intellectual property (IP) core library from Altera Corporation is shown in Figure 28. The main synthesis results are summarized in Table 11. Our 8-channel and 64channel FFTs consume approximately 35% more of the logic elements compared to the standard single channel FFT core. Considering we process 7 or 63 more channels of data, and only consume 35% more logic elements, this is quite an efficient implementation. The increase in resources is due to the hardware resources being reused for every channel. However, we can clearly see that the memory bits consumed is increasing with the increasing number of channels. These memory bits are consumed The 8-channel and 64-channel FFT processors utilize 128 9-bit embedded multipliers, while the standard single channel FFT core utilizes only 48 9-bit embedded multipliers. There are two reasons that make this difference. First, the standard single channel FFT core keeps a 24-bit data width for all the stages, while our FFT processors employed a data width increasing algorithm to achieve a better transform precision, which is shown in Figure 18. Second, the standard single channel FFT core re-used the multipliers in each butterfly. Re-using the multipliers would actually slow down our implementation of the FFT.
For the three FFT processors, we used the same Synopsys design constraints (SDC) file, which requires a clock rate of 200 MHz. The synthesis results show that the maximum clock rate of the standard single channel FFT IP core, the 8-channel FFT processor and the 64-channel FFT processor is 206 MHz, 156 MHz and 101 MHz, respectively. As we can see, the maximum clock rate decreases with the increasing of the number of channels. The reason for this is that more embedded memory blocks are involved with more channels, which eventually increases the length of the wire connections. The wire delay from the wire connection is the main constraint on the maximum clock rate. The 101 MHz maximum clock rate guarantees that the 64channel FFT processor can run safely at a lower clock rate, such as 50 MHz as we desire. To improve the resource consumption performance, we may lower the maximum clock restraint to 80 MHz, which will give the synthesizer more space to optimize the resource consumption. We tested the FFTs by using a combination of several sinusoid signals. The sinusoids with different frequencies were generated using Matlab and stored in a data file that was sent to the multi-channel FFT processor. In Figure 23,  The FPGA controller and digital signal processing module, the USB interface, Windows USB driver and application software were first tested and verified separately. The EEG monitoring system was also tested with a 128-channel configuration with simulated data in the FPGA. An 8-channel configuration was also tested with a real ECG recording. Further animal experiments are needed to test the seizure detector in a real environment.

Discussion
A distinct automatic seizure detector was developed to solve the special problem we met in the animal experiments. We emphazied the multi-channel, up to 128 channels, digital signal processing ability of the detector, a series of digital signal processing functional units were developed for this purpose. Thus, the system has the potential to be applied to real-time human seizure detection with up to 128 EEG channels, while most of the existing seizure detection systems only work for far fewer channels [44].
Accompanied with the automatic seizure detection system, we also developed a multi-channel EEG monitoring system. There are many commercial EEG monitoring systems on the market, such as Grass Comet and Aura EEG monitering systems, g.USB serial EEG monitoring systems. But these systems only allow the user to access the EEG data in the software level, while our system allows us to access and process the data at the hardware level, which significantly improves the real-time signal processing ability. With our system, we can implement and test many more applications which might not be pratical if we use the commercial systems.

Conclusion
An EEG automatic seizure detection system for rats, or any being, was implemented in an FPGA based embedded system. An EEG monitoring system was also developed. Both systems have the advantage of real-time signal processing ability for large numbers of channels.

Optimized TCRE Preamplifier Development
The precise passive circuit model for the TCRE should give the ability to design a preamplifier with optimization of the noise and cross talk rejection. The input-referred voltage noise of a low noise instrumentation amplifier is typically 50 nV/ Hz (with the gain 100, 0-100 Hz band), and the input-referred current noise is typically at 1 pA/ Hz , the noise model of the instrumentation amplifier is shown in Figure 31 [45]. The input-referred voltage noise is directly added to the input signal, while the input-referred current noise is coupled into the circuit by producing the corresponding voltage on the signal conditioning circuit and the sensor circuit, which is shown in Figure 32.
With the circuit models shown below in Figure 32, the noise of the preamplifier can be quantized easily by hand calculation or PSPICE simulation.
Proper usage of this noise quantization method should greatly help to design a low noise preamplifier for the TCRE. or generally for EEG electrodes, is that the crosstalk among channels must be rejected.
Crosstalk is the signal from one channel that creates an undesired signal on the other channels. For EEG applications, this phenomenon will directly decrease the spatial resolution of the recording. To lessen or avoid the crosstalk, some attention should be paid when laying out the printed circuit board (PCB) for the preamplifier. The common ground connection for the power supply lines, which is shown in Figure 33, must be prohibited. A star-connection, also shown in Figure 33, is a better alternative, while separate ground and power planes are mostly needed. Figure 33 Common ground connection (left) and star connection (right)