Limit cycles and pattern noise in single-stage delta-sigma modulators
Abstract
With in the last decade oversampling Delta-Sigma modulation techniques have gained significant importance in the field of analog-to-digital and digital-to-analog conversions. Oversampled data converters have some advantages over conventional Nyquist-rate converters. They provide an extremely wide dynamic range and also render the system very insensitive with regard to analog component nonidealities. Thus oversampling techniques have attracted the attention of circuit designers, since they enable the realization of high-resolution analog-to-digital converters (ADC's) without the need for a costly analog component trimming procedure. ^ But there remain two problems associated with ΔΣ modulators, which are not yet fully understood. One is the tonal behavior, which is responsible for non-white, discrete tones in the modulator output spectrum. Studying the cause of the tonal behavior will help us understand more about the resulting tonal noise spectra and will hopefully lead the way to a complete removal of these disturbing parasitics. ^ This dissertation is mostly concerned with the pattern noise problems occurring in single stage DSMs. First, the behavior of the DSM is modeled as a set of difference equations in the state space. By examining the difference of successive samples in the state space, the cause of the limit cycles in the DSM will be revealed. With the understanding of the mechanism of the limit cycles, all possible cases of limit cycles up to the point where our computational capacity saturates have been searched and found. Unfortunately, that limit does not include limit cycle sequences long enough to generate pattern noise in the passband. By simulating the 2nd, 3rd and 5th order DSM with arbitrary initial conditions and checking the resulting output sequences for their repetitiveness, many limit cycles could be detected. With sufficient numbers of such cases, the level of maximum frequency response of pattern noise was examined. The simulation has been done for the zero input case, which is believed to be the most important situation for pattern noise problems. Changes of limit cycle characteristics under small disturbing noise and non-ideal circuit environments have also been studied to check the effect thermal noise or a dithering source might have on the system. ^
Subject Area
Engineering, Electronics and Electrical
Recommended Citation
Deokhwan Hyun,
"Limit cycles and pattern noise in single-stage delta-sigma modulators"
(2000).
Dissertations and Master's Theses (Campus Access).
Paper AAI9999540.
http://digitalcommons.uri.edu/dissertations/AAI9999540