Parasitic error compensation in cascaded sigma-delta modulators
The purpose of this dissertation is to develop improved network structures for sigma-delta modulators implemented in switched-capacitor technology. Behavioral models of the non-ideal transconductor (OTA) are developed adapting earlier work in switched-capacitor filters. Common single-stage and multi-stage 3rd-order network structures with single-bit quantizers are investigated and their sensitivity with respect to OTA open loop gain and settling is compared. C-Ratio mismatch errors are also examined for specific cases where they are known to degrade operation. Performance bounds for several single stage and cascaded network structures are derived and compared with results obtained from behavioral simulations. Improvement for multi-stage structures composed of simple, first order modulators is investigated. This work will demonstrate that the 1-1 and the 1-1-1 cascaded structures can be made to approach the ideal dynamic range of the 2nd and 3rd order modulators, respectively, by digitally removing the noise induced by static analog circuit imperfections. This is accomplished by modifying the noise canceler to include estimates of amplifier gain and C-Ratio mismatch errors. This technique is expanded to include a 4th stage, forming a 1-1-1-1 cascade. In order to verify the method, a switched-capacitor version of a 1-1-1-1 cascade has been fabricated as a monolithic integrated circuit in a 1.2 μm CMOS process. The 1-1-1 cascade held a noise floor of −110 dB over a 15μVrms–400mV rms input signal amplitude range and the 1-1-1-1 cascade held a noise floor of −106 dB over the same input signal amplitude range. This result was confirmed for input signal frequencies of 300 Hz and 1 kHz. This is the first time a cascaded modulator with more than 3 stages has been successfully implemented. A 3rd-order-2 nd-order cascade (referred to as the 5-2 modulator) and a cascade of two nearly identical 3rd-order sections (referred to as the 6-3 modulator) are proposed and simulation results are presented. The higher order network structures allow for the placement of nulls (finite zeros) in the quantization noise spectrum at frequencies other than DC. This provides significant improvement in quantization noise attenuation at lower OSRs. (Abstract shortened by UMI.) ^
Engineering, Electronics and Electrical
Alan Joseph Davis,
"Parasitic error compensation in cascaded sigma-delta modulators"
Dissertations and Master's Theses (Campus Access).