On-chip timing measurement
In this dissertation, we propose an on-chip timing measurement technique. We design a TVC (time-to-voltage converter) circuit and demonstrate its application to on-chip phase locked loop jitter measurement and high-speed signal timing characterization. The core components of the TVC are a comparator with hysteresis, a capacitor, a binary counter and a charge pump. The charge pump consists of a current source and a current sink. During the measurement, a low frequency reference clock signal is used to control the current source to charge the capacitor with certain voltage offset, and the signal under measurement is used to control the current sink to discharge the same capacitor with the same voltage offset. With the binary number recorded by the digital counter, the targeted timing parameter can be easily figured out. ^ In our measurement circuit, the effects of fabrication process variations are minimized. So we can get very good measurement result. In PLL jitter measurement experiment, a 2MHz reference signal is applied to measure the jitter magnitude in PLL's 160MHz output signal. The measurement error is only 8%. In signal integrity verification experiment, a 5MHz reference signal is used to measure the rise time/fall time of 600MHz, 800MHz and 1GHz signals. The measurement error ranges from 5.5% to 13.1%. Compared with other existing on-chip timing measurement methodologies, our measurement circuit has better measurement accuracy. ^ The area of our measurement circuit is only 21% of that of phase locked loop. Considering phase locked loop is relatively a small circuit in a system, our measurement circuit is very compact and suited to be implemented on-chip. ^
Engineering, Electronics and Electrical
"On-chip timing measurement"
Dissertations and Master's Theses (Campus Access).