A monolithic phase locked loop frequency synthesizer for a 0.5um CMOS process

Praveen Reddy Parva, University of Rhode Island

Abstract

A Phase Locked Loop (PLL) frequency synthesizer is a closed loop high frequency generator, which employs a crystal oscillator with constant frequency. The reference signal (crystal) and the feedback signal are compared using a phase frequency detector (PFD). The filtered PFD output is subsequently fed to a voltage controlled oscillator (VCO), which generates the output frequency. In the ever increasing high performance (digital) systems, PLLs are frequently used to generate frequencies with high stability. ^ This thesis will detail the design of a phase locked loop frequency synthesizer using the cadence design kit in conjunction with the ONSEMI 0.5um CMOS technology. ^ All PLL units will be designed and simulated using the cadence design tool set available at ONSEMI. The Cadence tool has an embedded netlist generator, which will be used for this purpose. The netlist serves as a platform to simulate the design and the spectre waveform viewer will be employed to view the results. ^

Subject Area

Engineering, Electronics and Electrical

Recommended Citation

Praveen Reddy Parva, "A monolithic phase locked loop frequency synthesizer for a 0.5um CMOS process" (2011). Dissertations and Master's Theses (Campus Access). Paper AAI1503013.
http://digitalcommons.uri.edu/dissertations/AAI1503013

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