Research into computer hardware acceleration of data reduction and SVMs

Jason Kane, University of Rhode Island

Abstract

Yearly increases in computer performance have diminished as of late, mostly due to the inability of transistors, the building blocks of computers, to deliver the same rate of performance seen in the 1980’s and 90’s. Shifting away from traditional CPU design, accelerator architectures have been shown to offer a potentially untapped solution. These architectures implement unique, custom hardware to increase the speed of certain tasking, such as graphics processing. The studies undertaken for this dissertation examine the ability of unique accelerator hardware to provide improved power and speed performance over traditional means, with an emphasis on classification tasking. (Abstract shortened by ProQuest.)^

Subject Area

Computer engineering|Engineering

Recommended Citation

Jason Kane, "Research into computer hardware acceleration of data reduction and SVMs" (2016). Dissertations and Master's Theses (Campus Access). Paper AAI10100310.
http://digitalcommons.uri.edu/dissertations/AAI10100310

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